In a conventional characterization vehicle (CV), a plurality of test structures are fabricated on an integrated circuit (IC) chip. As is known in the art, an IC chip is typically formed by performing a series of processing steps (e.g., etching layers to form structures, doping layers with chemicals, and depositing materials on top of layers) on a semiconductor substrate (e.g., silicon substrate). Through such processing of the semiconductor substrate, an integrated circuit (comprising transistors, capacitors, resistors, etc. interconnected by conductive traces) is formed on and within the semiconductor substrate. An IC chip, once fabricated, is typically housed within a semiconductor package having pins or leads that electrically connect the IC chip to landing/bonding pads external to the semiconductor package.
Each test structure of the IC chip may be designed in accordance with a design of experiment (DOE). A key purpose of the DOE is to stress the manufacturing process by taking the test structures to process corners and beyond (e.g., by violating one or more design rules).